SMT

Optimizing SMT stencil design based on PCB layout

Optimizing SMT stencil design based on PCB layout. Orignal Article by: Ben Scott, Datum Alloys; Chrys Shea, Shea Engineering Services; and Carol Wood, Alpha Stencils
Optimizing SMT stencil design

This article was presented at /MAPS New England 2014 Symposium and Expo held on May 6 in Boxboro, MA

Article published in Global SMT & Packaging – May 2015 

With so many different stencil technologies out there, how is a stencil designer to know which will work best on any given product?

Just like almost everything else related to SMT assembly, it all depends on the board layout. Component type and location, population density, and PTH presence all factor into selecting the best materials, manufacturing processes, and performance-enhancing coatings to get the best possible results in the solder paste printing process.

ARTE - Area Ratio and Transfer Efficiency Calculator

Optimizing SMT stencil design

Excel program reads Gerber file, user inputs foil thickness

– Automatically calculates ARs & TEs
– Warns at low AR (selected by user)
– Acknowledges AR corrections
– Can change aperture size or foil thickness on the fly and immediately see effects
– Can add preforms into calculation
Predicts individual deposit volumes
– Predicts total amount of paste deposited on PCB

Figure 1. Screenshot of ARTE.

Design review

Design review PCB layout drives the primary consid­erations of stencil design: foil thickness and aperture sizes. Larger components, through-hole connectors, and components with known coplanarity or warpage issues require larger paste deposits from thicker stencil foils, whereas smaller components with finer pitch I/Os push the area ratio limits and drive the use of thinner foils. When both appear in the same layout, they clash, but there are a number of options for accommodating the conflicting require­ments.

The first step in resolving the conflicts is identifying them. Automated design­checker software like Alpha’s ARTE system reads a stencil’s Gerber file and calculates all the area ratios, issuing warnings about those below a threshold set by the user, often in the 0.60 to 0.66 range. 

In addition to basic design rule checking, ARTE also uses transfer efficiency equations devel­oped in Alpha’s solder paste labs to predict transfer efficiencies and deposit volumes. 

When both large and smaller/fine picth components appear in the same layout, they clash, but there are a number of options for accommodating the conflicting requirements.

This unique capability enables the user to quickly investigate numerous aspects of the stencil’s design, including the effects of changing foil thickness or aperture size and stepping stencils. It can also suggest the best solder preform to use to compensate for thinning foils and calculate the solder volume difference based on its suggestion or on the user’s own selection. 

A screenshot of ARTE is shown in Figure 1.

Stepped Stencils

Often times stepping stencils provides the optimum solution to conflicting thickness requirements. Stencils can be stepped a number of ways:

• Step Up: Thickens stencil locally
• Step Down: Thins stencil locally
• Top or Bottom side steps, or both
• “Stepless” steps: Smooth the tran­sition ( used with enclosed print heads)
• Angled steps: Reduce squeegee damage (also used with enclosed print heads)
• Cavity relief: on the PCB side of the stencil to accommodate labels or other topographical features

Design guidelines for steps include a maximum step height or depth of 2 mil (50 µm) per step to maintain good fill pres­sure, and a minimum keepout perimeter of 25 mil (625 µm) around the apertures. The farther away from the apertures the step can be located, the better. It will allow for better squeegee blade deflection into the step, and keep the paste that always builds up and dries out near the step wall farther away from the apertures (Figure 2).

Figure 2. Larger keepout zones keep dried paste buildup in the corner of the pocket, away from the apertures.
Figure 2. Larger keepout zones keep dried paste buildup in the corner of the pocket, away from the apertures.
Datum PhD 304 Stainless SteelDatum FG (Fine Grain)
304 Stainless Steel
Miniaturized or high-density assembly ✔
Area ratios <0.66 ✔
General SMT, lead pitches ≥ 0.5 mm, leadless✔
Stepped stencil for µBGA, CSP, QFN, BTC✔
Uniform foil thickness ≥ 150 µm ✔
Powder size Type 4,5,6 ✔
Powder size Type 3 ✔✔
Table 1. When to select PhD or FG.

Components that do not necessarily require steps but can accept them are often included in the stepped area to maintain the keepout zone. Other layout options include clustering components that require steps to create fewer, larger stepped areas instead of many smaller ones.
If the desired step depth is only 1 mil (25 µm), then an incrementally-sized foil may provide the ideal solution. 

 Alpha pro­vides nickel foils that are grown in their electroforming tanks in half-mil (12.5µm) increments: 3.5, 4.5, 5.5 or 6.5 mils thick. Nickel foils not only offer these sub-1 mil incremental thicknesses; they also offer high durability for processes that must run excessive print pressures.

Foil thickness, material selection and manufacturing process

Stainless steel (SS) is the material of choice, except when special circumstances dic­tate nickel. Standard SS is the least expensive option, but can be prone to thickness variations, inclusions or other flaws in the material, and warping or bowing in reac­tion to the heat generated by laser cutting. Premium SS manufactured specifically for SMT stencils by Datum Alloys is precision rolled to maintain very tight thickness tol­erances and is stress relieved to prevent distortion from the heat of cutting. In addition to the popular stress-relieved SS alloy known as PhD, Datum also offers a fine grain (FG) SS that reduces the typical grain size by an order of magnitude (Figure 3). The finer grains produce smoother stencil walls and crisper steps. Many high precision stencil printing processes depend upon it. 

When should a designer choose PhD or FG? The considerations are shown in Table 1. Well-tuned modern laser cutters pro­duce high accuracy stencils. If nickel is required, laser cutting the apertures into a formed nickel “blank” will likely produce a more accurate stencil than most electro­forming process. It will also save lead time and cost. Regardless of the foil material, the overall performance of a stencil is heavily dependent on the quality of the aperture wall, and many studies have correlated wall roughness to print performance.
grain structure
Figure 3. Fine grain stainless steel reduces the typical grain size by an order of mag­nitude.

Nickel plating and electropolishing

Secondary processes like nickel plat­ing over SS or electropolishing the SS are sometimes used in conjunction with laser cutting. Plating nickel over SS is supposed to add the durability of nickel to the pre­cision of SS to combine the best qualities of both. In recent tests, it did not fare as well as laser-cut premium SS in print per­formance; the nickel plating lowered area ratios both by increasing the foil thick­ness by and reducing the aperture sizes. Differences as large as 0.4 mils in aperture size and foil thickness were noted.

Electropolishing was very popular in the early days of laser cutting SS because it removed the scalloped peaks in the walls produced by the wider laser beams of the original cutting equipment. In contrast to the nickel plating process that adds mate­rial to the original stencil, electropolishing removes small amounts of it. In addition to smoothing the walls, the electropolish­ing process actually opens up the apertures and thins the stencil a bit, giving it a slight area ratio advantage, helping it demon­strate better transfer efficiency than non­electropolished stencils.

Unfortunately, it also tends to round the corners of the aper­tures to compromise gasketing and induce more print volume variation (Figure 4). It is not often used anymore-modern lasers can cut cleaner, smoother walls from more consistent, laser-friendly materials and electropolishing is not necessary. A good laser cut achieved with a well calibrated and maintained cutter will produce walls smooth enough to provide optimal paste transfer performance without requiring any secondary processes.

Electropolishing

Figure 4. Effect of electropolishing on aperature geometry.

Nanocoating

Nanocoating can substantially boost pro­ductivity. This special repellency treat­ment is applied to the finished stencil, and prevents the flux from spreading on the bottom surface, keeping it cleaner for longer. The cleaner stencil bottom:

• Gaskets better
• Produces crisper prints
• Extends under wipe intervals
• Cleans easier
• Saves money on wiper paper, and (sometimes) solvent and cycle time

QFN and 0201s after 10 prints with no wipe

Same board, same stencil, same print stroke

nanocoating-stencil-untreated

Untreated stencil

Flux wicks out on the bottom surface away from the apertures
nanocoating-stencil-treated

Treated stencil

Flux is repelled from the bottom surface and is contained primarily within the apertures
Figure 5. Nanocoating repels flux on stencil’s bottom surface.

Figure 5 shows the stencil apertures for QFNs after 10 prints with and without Aculon’s NanoClear nanocoating. 

Figure 6 shows the resultant prints. The difference in print definition is visible in the deposits for the thermal pad and the wet-bridged 0201s.

When nanocoatings were first intro­duced, their utilization was focused on improving fine feature printing processes. Continued research on their applica­tion has revealed that they will enhance just about any print process, regardless of PCB layout. Over the past year, their cost has been reduced and their availability improved, and as users continue to docu­ment the increases in quality and pro­ductivity, their popularity will continue to grow.
nanocoated stencil
Figure 6. QFN and 0201s after 10 prints with no wipe: same board, same stencil, same print stroke. Untreated left, nanocoated right.

Summary

Optimizing stencil performance based on a PCB layout is a straightforward process, but requires a number of decisions based on the features of the layout. The first, and most critical, choice is on foil thickness. Typical SMT processes use 5 mil (125 µm) foils, but some components require larger deposits that drive thicker foils and some require smaller, more precise deposits that require thinner foils. The stencil designer needs to make sure the foil thickness and aperture sizes do not violate area ratio rules, and stencil design analysis software like ARTE speeds the calculation process while preventing errors.
Sometimes foils must be stepped to accommodate multiple thicknesses. Stepping guidelines are available to help insure the best possible print quality; if the guidelines are compromised, the print quality is likely to suffer. Steps of lmil or less may be addressed by using an incre­mental size nickel foil; steps or 2 mil or greater should use Fine Grain SS. Other considerations for using Fine Grain SS include foil thicknesses of 5 mil (125 µm) or less, devices with pitches of 20 mil (0.5 mm) or less, high density or highly minia­turized layouts, or area ratios less than 0.66.
pcb-layout
Figure 7. PCB layout drives the stencil print process.
Secondary processes like nickel plat­ing over SS or electropolishing have not been shown to improve overall print per­formance in recent studies and typically should not be a factor in stencil design or manufacturing decisions. Rather, the cut quality that a supplier is capable of provid­ing should be a larger consideration. The smoother walls created by the combination of specialized SS and modern laser cut­ters have shown to produce the best print quality in successive tests, consistently out­performing every other stencil fabrication technology available. The finer the feature, the more important cut quality becomes­l 206s are more forgiving than 0201s; as are QFPs compared to QFNs. Nanocoating improves quality and cost by keeping the PCB side of the stencil clean, reducing underwipe frequency and improving print definition. It can positively impact any solder paste printing process, regardless of PCB layout.
Figure 7 depicts the decision path and its factors, and indicates a feedback loop for Design for Manufacturability inputs. Understanding how the PCB layout affects the entire print process-from stencil design to production yields-enables development teams to incorporate cost­conscious manufacturing decisions in early stages of product design, where they have the greatest impact.
Original Article

Ben Scott is the CEO of Datum Alloys, the # 1 worldwide supplier of SMT stencil mate­rials; uk.sales@datumalloys.com

Chrys Shea is the president of Shea Engineering Services, an electronics manu­facturing consulting firm; chrys@sheaengi­neering.com

Carol Wood is the North American Operations Manager for Alpha stencils, combining Alpha’s global knowledge, experi­ence and service to produce over half a mil­lion stencils worldwide; cjwood@alent.com

Modern SMT Considerations:
While the principles outlined above remain valid, stencil design requirements have evolved significantly with the widespread adoption of lead-free processes and ultra-fine-pitch components. Modern assemblies routinely use 0201/01005 passives and ≤0.4 mm pitch devices, where tighter tolerances, higher paste viscosity, and increased surface tension make paste release more challenging. 

As a result, designers should apply stricter control of area ratio (≥0.66) and aspect ratio (≥1.5), consider thinner or step stencils for mixed-technology boards, and use advanced features such as tapered apertures, rounded corners, and nano-coated stencils to improve release consistency. Additionally, stencil design is now closely tied to process control, with SPI feedback, cleaning frequency, and printer capability all influencing final performance. These factors should be incorporated alongside the original guidelines to achieve robust yields in modern SMT production.

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